1. Field of the Invention
This invention relates to a method for fabrication of a MIS device and more particularly an offset gate MIS device.
2. Description of the Prior Art
According to the conventional method of fabricating a silicon gate MISFET, a gate electrode pattern is formed by photoetching on a polycrystalline silicon layer which lies on a gate insulator film, the unwanted portion of the gate insulator film is removed in a self-alignment fashion by using the gate electrode as a mask, and source and drain regions are formed through the selective diffusion of impurities. Consequently, the integration density and the characteristics, especially the operating speed, can be considerably improved in comparison with those of an aluminum gate MISFET.
However, according to the conventional method for fabrication f a silicon gate MISFET, the source and drain regions are formed by using the gate electrode as a mask so that the drain region of offset configuration cannot be formed. Accordingly, an inverse electric field due to the substrate-drain junction and the gate-drain field are applied near the portion of the drain region beneath the gate electrode so that a depletion or space charge layer extending from the drain toward the substrate does not expand sufficiently near the surface of the substrate. As a result, local concentrations of field are generated to be causative of avalanche breakdowns. This makes difficult the production of devices having a high breakdown voltage. This weakpoint is therefore fatal to a silicon gate MISFET having various excellent characteristics and merits.
There is known an aluminum gate MISFET in which source and drain regions of low impurity concentration are provided to insure good ohmic contact with source and drain electrodes, and source and drain extensions of high impurity concentration are provided to improve the source-drain breakdown voltage (see U.S. Pat. No. 3,959,025).
A silicon gate MISFET having a drain region of offset configuration is known in U.S. Pat. No. 3,909,306. In accordance with the fabrication method shown in this patent, a silicon oxide layer formed on a N-type silicon substrate is partially removed to diffuse P-type impurities into the exposed surface of the substrate through inpurity ion implantation and heat treatment so that a P-type drain region having a low impurity concentration and a thickness of 5-10.mu. is formed. During the diffusion, a silicon oxide layer is formed on the substrate surface in which the P-type drain region is formed. Next, there are removed those portions of the silicon oxide layer overlying a central surface portion of the P-type low impurity concentration drain region and that surface portion of the substrate in which a source region and a channel region are to be formed. The exposed substrate surface is thereafter oxidized to form a gate oxide film of silicon oxide. A polycrystalline silicon layer is formed on the gate oxide film and the remaining silicon oxide layer. The polycrystalline silicon layer is then partially removed so that a portion thereof on the channel region remains for forming a gate electrode. Further, the gate oxide film is partially removed so that the surface portion of the substrate for forming the source region and the central surface portion of the P-type low impurity concentration drain region are exposed. Thereafter, P-type impurities are diffused into the exposed substrate surface so that a P.sup.+ -type source region (P-type high impurity concentration source region) and a P.sup.+ -type drain region (P-type high impurity concentration drain region) in the P-type low impurity concentration drain region are formed with a thickness of about 1.mu.. Thus, The gate electrode is formed to bridge the source region and the drain region of low impurity concentration but to be spaced from the drain region of high impurity concentration, so that a depletion layer extends sufficiently into the drain region of the low impurity concentration to prevent electric field concentration. However, the above-explained fabrication method has the problems that the steps for fabrication are quite complicated and the advantage of self-alignment is not effectively utilized.